1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of isolation regions and/or stress regions.
2) Description of the Prior Art
As the channel length continues to shrink, substrate engineering becomes one of the key methods to improve the performance of CMOS devices. This is achieved by stress enhancement on the NFET or PFET.
Another important aspect in substrate engineering is to form adequate isolation features between the devices to suppress the effect of latch-up. Latch-up is a phenomenon that establishes a very low resistance path between the VDD and VSS power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning or even destroy itself due to high power dissipation.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 4,533,430: Process for forming slots having near vertical sidewalls at their upper extremities—Inventor: Bower, Robert W.; Los Gatos, Calif.
U.S. Pat. No. 6,313,008: Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon—Inventor: Leung, Ying Keung; Hong Kong, China.
U.S. Pat. No. 6,800,535: Method for forming bottle-shaped trenches—Title: Forming bottle trench—Inventor: Tsai, Tzu-Ching; Taoyuan.
U.S. Pat. No. 5,915,192: Method for forming shallow trench isolation—Inventor: Liaw, Jhon-Jhy; San Chung, Taiwan.
U.S. Pat. No. 6,716,757: Method for forming bottle trenches—Title: Method to form a bottle-shaped trench—Inventor: Lin, Shian-Jyh.